A semiconductor wafer is processed by a semiconductor manufacturer to form various integrated circuits (IC) in different regions of the wafer. Pattern density variations over the different regions causes various issues including critical dimension (CD) variation or CD uniformity. When the semiconductor fabrication scales down to advanced technologies, such as 45 nm, 32 nm, or 28 nm, the IC features are more sensitive to the CD variations and uniformity. For example, dense lines and isolated lines are common in IC layout and cannot be avoided by the design rules. The sudden variation of local pattern density surrounded may cause the distortion of IC feature, referred to as a necking or bridge issue. Due to the limited surrounding, the use of scattering bars is often ineffective to reduce this issue. Re-targeting the width of the IC feature is also limited by side space availability. Therefore, there is a need of a new integrated circuit pattern and the method masking the same to address the issue.